Synchro-to-digital converter

ABSTRACT

A shaft-angle to digital-data converter that compensates for the nonlinear relationship between a given shaft angle theta and its trigonometric function as represented by first and second analog voltage signals E1, E2. The converter operates over the shaft angle theta range of 0* to 45* having a maximum error of 5 minutes of arc. The 45* range is divided into three angular segments with appropriate resistors selectively coupled to an operational amplifier to control its gain so as to generate the variable bias signal for biasing a resistor ladder in the desired manner. Selected bits of an approximated data word selectively couple-in the appropriate resistors while all the bits of the approximated data word are coupled to the resistor ladder. The current signal output of the resistor ladder and a current signal that is generated by the first analog voltage signal E1 are compared by a comparator which comparison provides, as an output, a binary signal. The binary signal increments or decrements the bits of the approximated data word achieving a final data word using the successive approximation method. The final data word represents the digital value theta D of the shaft angle theta as represented by the first and second analog voltage signals E1, E2.

United States Patent Metz v Aug. 29, 1972 [72] Inventor:

[54] I 'SYNCHRO-TO -DIGITAL CONVERTER Louis C. Metz, St. Paul, Minn.

[73] Assignee: Sperry Rand Corporation, New

York, NY.

[22] Filed: June 10, 1970 211 Appl. No.: 45,079

52 US. cl. ..340/347 sY 3,516,084 6/1970 Sacks et al..'.;. ..340/347 Primary Examiner-Maynard R. Wilbur Assistant Examiner-Charles D.- Miller Att0meyKenneth T. Grace, Thomas 'J. Nikolai and Job P. Dority OCTANT DETECTOR OCTANT MULTIPLEXER I E, E2 SELECTOR cu, NETWORK c|o.co9

DATA REGISTER o CONTROL 0GI C [5 ABSTRACT A shafi-angle to digital-data converter that compensates for the nonlinear relationship between a given shaft angle 0 and its trigonometric function as represented by first and second analog voltage signals E E The converter operates over the shaft angle 0 range of 0 to 45 having a maximum error of 5 minutes of arc. The 45 range is divided into three angular segments with appropriate resistors selectively coupled to an operational amplifier to control its gain so as to generate the variable bias signal for biasing a resistor ladder in the desired manner. Selected bits of an approximated data word selectively couple-in the appropriate resistors while all the bits of the approximated data word are coupled to the resistor ladder. The current signal output of the resistor ladder and a currentsignal that is generated by the first analog voltage signal B are compared by a comparator which comparison provides, as an output, a binary signal. The binary signal increments or decrements the bits of theapproximated data word achieving a final data word using the successive approximation method. The

final data word represents the digital value 0,, of the shaft angle 0 as represented by the first and second analog voltage signals E E 3Claims,5DrawingFigures LINEARIZING COMPARATOR NETWORK PKTENTEBmszs m2 sum 2 or 3 0-004 JOmFZOU 558m ES mmoo 4 A m mwi u BY M t/ ATTORNEY 1 SYNCHRO-TO-DI'GITAL CONVERTER BACKGROUND OF THE INVENTION The present invention relates to devices for converting an angular quantity, such as the angle of rotation of a synchro element, to its digital equivalent. Such devices have been characterized into many classes see the series of five'publications Synchro-to-Digital Converters, Hermann Schmid, Electronic Design 6, beginning Mar. 15, I970 and are a specific class of analog-to-digital converters.

The present invention involves the incorporation of a resistance network in an otherwise old converter system for linearizing the otherwise nonlinear relationship of a given shaft angle and its trigonometric function as represented by first and second analog voltage signals K sin 0 andK cos 0. The converter system includes an input multiplexer that scans a plurality of synchro outputvoltage 'signalsK sin 0, K cos 0 that are representations of the synchro shaft angle 0. The two scanned signals are coupled to a sample and hold device and thenceto an octant detector that determines the particularoctant in which the particular shaft angle 0 lies (and which, in doing so, determines the relative magnitudes of the two scanned signals). The smaller signal, designated E is coupled to a first input terminal while the larger signal, designated E is coupled to a second input terminal.

From the first andsecond signals E E a reference signal E, is generated that biases a-resistance ladder network. Bits from a data register, holding'an approximated data word, are coupled to the resistance ladder network generating an output current signal I that at a comparator is compared to a current signal I generated by signal E The comparator compares I to generating a current signal 1 i.e., I, I i i which through the comparator alternatively couples a binary signal 1" or 0" to control logic which then adjusts the approximated dataword held in the data register. Through the successiveapproximation method see the'publication Specifying'Analog-to-Digital Converters, Jay Freeman, The Electronic Engineer, June 1968, pages 44 48 particularly FIGS. 1, 2 page 45 the approximated data word is stepwise corrected to the final data word representing 0 SUMMARY OF THE INVENTION The present invention-incorporates a Iinearizing network in an otherwise old analog digital converter system for linearizing the otherwise nonlinear relationship between a givenshaft angle 0 and its trigonometric function. The linearizing network includes a plurality of resistors that through associated analog switches selectively couple the voltage signals +E, and +E to an operational amplifier generating a reference signal -E The reference signal E biases the 'R, 2R resistance ladder network the steps of which are coupled to and enabled by the associated l bits of the approximated data word held in a data register. The resistance ladder network generates a current signal I, which is compared to a current signal +1, provided by E The comparison generates a third current signal i I which drives a comparator providing, alternatively, binary output signals l or 0 if the comparison signal is H or l respectively.

The binary signal drives control logic which adjusts the bits of the approximated data word in the corresponding manner. The three highest ordered bits, C1 1, C10, C09 of the approximated data word, through switching logic, condition, i.e., enable or disable, the analog switches which in turn, by changing the gain of an operational amplifier, change the reference voltage E and the comparison signal :1 The process of successive approximation continues until the lowest ordered bit in the approximated data word is set or cleared, i.e., is a l or a 0, providing the final digital data 'word that represents the value 0 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an analog-to-digital converter system into which the present invention is incorporated.

FIG. 2 is a detailed circuit schematic of the linearizing network of the present invention.

FIG. 3 is the equivalent circuit schematic of the linearizi ng circuit ofFlG Z for the range 0 56 22. 5.

W FIG? [is the equivalent circuit schematic of the lineariz ing circuit of FIG. 2 for the rangeZ .5 0

FIG. 5 is the equivalent circuit schematic of the linearizirrg circuit of FIG. 2 for the range 33.75 s 6 s DESCRIPTION OF THE PREFERRED EMBODIMENT With particular reference to FIG. 1 there is presented a block diagram of an analog-to-digital converter system into which the present invention is incorporated. The converter system includes an input multiplexer 10 that scans a plurality of synchros 12, 14, l6, 18 each providing their associated output voltage signals K sin 0, K cos 0 which are representations of the synchro shaft angle 0. The twoscanned signals are coupled to a sample and hold device in input multiplexer 10 and thence to an octant detector 20 that determines the particular octant in which the particular shaft angle 0 lies and to an E E selector 22. The smaller signal, designated E is coupled to a first input terminal of linearizing network 24 while the larger signal, designated E is coupled to a second input terminal of linearizing network 24.

From the first and second signals E E a reference signal E is generated that biases a resistance ladder network 26. Bits from a data register 28, holding an approximated data word, are coupled to the resistance ladder network 26 generating an output current signal -1 that at a comparator 30 is compared to a current signal I generated by signal E,. The comparator 30 compares I, to I, generating a current signal I i.e., I, I i 1 which throughthe comparator 30 alternatively couples a binary signal 1 or 0 to control logic 32 which then adjusts the bits of the approximated data word held in data register 28. Through the successive approximation method the approximated data word is stepwise corrected to the final data word representing 0 With particular reference to FIG. 2 there is presented a more detailed circuit schematic of the linearizing network 24 and its relationship with resistance ladder network 26, data register 28, comparator 30 and control logic 32. Linearizing network 24 includes a plurality of analog switches 40, 42, 44, 46 see the publication Electronic Analog Switches", Hermann Schmid, Electro-Technology, June 1968, pages 35 50 -that are selectively enabled or disabled by switch logic 48 under control of the highest ordered bits C11, C10, C09, of the data word held in data register 28. Switch logic 48, in accordance with the binary signal "1" or of the highest ordered bits C11, C10, C09 of the approximated 12-bit data word (bits C11 C00) in data register 28, enables or disables selected ones of analog switches 40, 42, 44, 46 in accordance with Table A.

As an example, for the start of the successive approximation method bit C11 is set to a 1 while all other bits are cleared to a 0 representing an initial one-half full scale approximated data word. Bits C11, C10, C09 enable analog switches 40, 42 and disable analog switches 44, 46 whereupon resistors R R.,, R are coupled in parallel acrossnodes 51, 52 and only resistor R is coupled across nodes 55, 56. These resistance combinations couple voltage signals E E to the input of operational amplifier 50 which along with feedback resistor R generate a reference voltage E which is coupled to the input of resistance ladder network 26. These circuits associated with resistors R R R and resistors R R R are utilized to compensate for the nonlinear relationship existing between the given shaft angle 0 and its equivalent trigonometric function.

The conversion technique is used over the range 0 to while in order to limit the inherent error to 5 minutes of arc the 45 range is divided into three angular segments:

33.75 s 6 s 45. These angular segments are established by the selective enabling or disabling of analog switches 40, 42. 44, 46 under control of switch logic 48 and as determined by the binary signal 1 or 0" of the three highest ordered bits C11. C10, C09 of the approximated data word in data register 28. The analog switches select various combinations of resistance values in the linearizing network which, in turn, control the overall gain of operational amplifier 50. The output of operational amplifier 50 couples the reference voltage E to the input of resistance ladder network 26 for biasing the resistance ladder in the desired manner. The resistance ladder is scaled under control of the bits C11-C00 of the approximated data word in data register 28 coupling an output current to node 58 of comparator 30. Concurrently, voltage +E, through Resistor R, couples a current signal +11 to node 58 providing a comparison current signal :l

as an input to comparator 30. Comparator 30 for a comparison current signal +13 couples a l or for a comparison current signal 1 couples a 0 to control logic 32 incrementing or decrementing, respectively, the bits of the approximated data word in data register 28. Through changes in bits C11.C10, C09 switch logic 48 enables or disables analog switches 40, 42, 44, 46 effecting a corresponding change in reference voltage E3 while all bits C11-C00 scale the resistance ladder network 26 to effect corresponding changes in -l2 and, consequently, 1

The linearizing network 24 operates under the following theory and conditions. Using the relationship,

0 =Shaft Angle where 0 is constrained to the following limits 0 0 s 45.

with the two input voltage signals from the synchro being E, K sin 0 E, =K cos 0 the value of 0,, (B is obtained from the following equation (1),

aE +bE (1) p which yields Equation (2),

N sin 6 a sin 0+b cos 0X40 (2) over the constrained limits.

To limit the inherent error in equation (2) to 5 minutes or less of arc over the constrained limits, the 45 range is divided into three angular segments each having its own values for the parameters a and b as listed in Table In the linearizing network 24 of FIG. 2:

the values of resistors R R R R and the conditions of analog switches 40, 42 determine the parameter a;

the values of resistors R R R R and the conditions of analog switches 44, 46 determine the parameter b. Further, the analog switches 40, 42, 44, 46 are selectively enabled ON, i.e., closed switch, or disabled OFF, i.e., open switch, under control of switch logic 48 as determined by the highest ordered bits C11, C10, C09 of the approximated data word bits Cl 1 v 14 C00 in data register 28, i.e., the value of 0 so that the parameters a and b have the values noted in Table B.

The reference voltage E:,, which is the output of operational amplifier 50 and the input of resistance ladder network 26, is represented by the equation (3 Reference voltage -E,is coupled to the comparator 30 null point 58 through linear R, 2R resistance ladder network 26 whose transfer ratio is proportional to (0.5 is equivalent to 45) and whose output impedance is equal to 0.5 resistor R,. When comparator 30 input I,

is null or zero, current signal I, is represented by,

I; o r

Substituting in equation (3) gives equation (4),

(a ,+bE2 D R,45 (4 15 With the 66m m650 input at null,

. i t r 1 and, r

and as then,

Substituting in equations (4), (5

E, (aE,+ E2)oD R, R,45 0

0 E, (aE,+bE %:0 E,= (aE l -bE E, 451 a aE +bE D ,o

which is equation (1). This value of 0 is subsequently added to or subtracted from the quadrant angle determined by octant selector 20 of FIG. 1.

With particular reference to FIGS. 3, 4, 5 there are presented the equivalent circuit schematics for the three angular segments,

0 s 0 s 22.5 FIG. 3,

33.75 6 45 no.5, as determined by the enabling or disabling of analog switches 40, 42, 44, 46 by switch logic 48 under control of the three highest ordered bits C11, C10, C09 of the approximated data word in data register 28, and as detailed in Table A.

What is claimed is:

1. In a shaft-angle to digital-data converter wherein E, and E signals which are representative of first and second trigonometric functions, respectively, of said shaft angle 0, are through the successive approximation method converted to a multibit data word held in a data register, which data word is representative of said shaft angle 0, using a ladder network having a reference -E, signal input for converting the approximated data word held in the data register to a I, signal and a resistor network for converting said E, signal to a +1, signal, a comparator for comparing said +1, and I, signals and generatinga binary output that is representative of said comparison, and control logic for-changing said approximated data word in-said datargister'in response to said binary output, the-improvement comprising:

E, signal means for providing an E, voltage signal that isrepresentative of a first trigonometric function of said shaft angle 0;

E signal means for providing an E, voltage signal that is representative of a second trigonometric function of said shaft angle 0;

amplifier means for providing at its output a E, voltage signal in response to said E, and E, voltage signals;

first and second switch means coupled to said E,

signal means;

firstand second resistor means each coupling the associated first and second switch means, respectively, to the input of said amplifier means;

third and fourth switch means coupled to said E,

, signal means; I v

third and fourth resistor means,each coupling the associated third and fourth switch means, respectively, to the input of said amplifier means;

+1, signal means coupled to said'E, signal means for generating a +1, current signal;

switch logic means selectively enabling said first,

second, third and fourth switch means for changing the gain of said amplifier means and generating a corresponding change in said E voltage signal;

means coupled to said amplifier means and generating a -1 current signal from said -E, voltage signal and coupled to said +1, signal means and responding to the difference between said +1, and I current signals for controlling said switch logic means.

2. In a shaft-angle to digital-data converter wherein E, and E signals which are representative of first and second trigonometric functions, respectively, of said shaft angle 0, are through the successive approximation method converted to a multibit data word held in a data register, which data word is representative of said shaft angle 6, using a ladder network having a reference E, signal input for converting the approximated data word held in the data register to a -1 signal and a resistor network for converting said E, signal to a +l signal, a comparator for comparing said +1, and --I signals and generating a binary output that is representative of said comparison, and control logic for changing said approximated data word in said data register in response to said binary output, the improvement comprising:

E, signal means for providing an E, voltage signal that is representative of a first trigonometric function of said shaft angle 0;

E signal means for providing an E voltage signal that is representative of a second trigonometric function of said shaft angle 0; I

amplifier means for providing at its output a E voltage signal in response to said E, and E voltage signals;

first and second switch means coupled to said E,

signalmeans;

first and second resistor means each coupling the associated first and second switch means, respectively, to the input of said amplifier means;

third and fourth switch means coupled'to said 1:,

signal means;

' third and fourth resistor means, each coupling the associated third and fourth switch means, respective ly, to the input of said amplifier means;

fifth resistor means coupling said E, signal means to enabling said first, second, third and fourth switch means in response to said approximated data word for changing the gain of said amplifier means and coupling a' correspondingly changed --E, signal to said ladder network.

.3. in a shaft-angle to digital-data converter, the apparatus comprising:

E signal means for providing, an E; voltage signal that is representative .of a first trigonometric function ofsaid shaft angle 0; t

E, signal means for providing an E voltage-signal.

that is representative of a second trigonometric function of said shaft angle 0;

amplifier means for providing at its output a' E, voltage signal in response to said E, and E, voltage signals;

a first plurality of switch means coupled to said E signal means;

a first plurality of resistor means for parallely coupling an associated one of said first plurality of switch means to the input of said amplifier means;

'a second plurality of switch means coupled to said E;

signal means;

a second plurality of resistor means for parallely coupling an associated one of said second plurality of switch means to the input of said amplifier means; i p

a resistor ladder network for providing at its output a -l, current signal;

means coupling said -15, voltage signal output of said amplifier means to the input of said ladder network;

a comparator;

means coupling said -I,current signal output of said ladder network to said comparator;

means including a resistor means for coupling a +1, current signal from said E, signal means to said comparator; A

said comparator comparing said +1 and -I, current signals and alternatively providing ,at its output a first and a second one of a binary signal that is representative of said comparison;

control logic means; v

data register means for holding a multibit data word;

means for coupling said binary signal to said control logic means;

means coupling said control logic means to said data register means for changing said multibit data word held in said data register means inresponse to said binary signal;

means coupling said data register means to said first and second plurality of switch means for selectively enabling said first and second plurality of switch ssrtsrs sa daasasrsacram; as -E, voltage signal in response thereto; and,

means coupling said data register means to said ladder network for enabling both said changing multibit data word held in said data register means and said changing E, voltage signal to generate a corresponding change in said --I, current signal.

t k l 

1. In a shaft-angle to digital-data converter wherein E1 and E2 signals which are representative of first and second trigonometric functions, respectively, of said shaft angle theta , are through the successive approximation method converted to a multibit data word held in a data register, which data word is representative of said shaft angle theta , using a ladder network having a reference -E3 signal input for converting the approximated data word held in the data register to a -I2 signal and a resistor network for converting said E1 signal to a +I1 signal, a comparator for comparing said +I1 and -I2 signals and generating a binary output that is representative of said comparison, and control logic for changing said approximated data word in said data register in response to said binary output, the improvement comprising: E1 signal means for providing an E1 voltage signal that is representative of a first trigonometric function of said shaft angle theta ; E2 signal means for providing an E2 voltage signal that is representative of a second trigonometric function of said shaft angle theta ; amplifier means for providing at its output a -E3 voltage signal in response to said E1 and E2 voltage signals; first and second switch means coupled to said E1 signal means; first and second resistor means each coupling the associated first and second switch means, respectively, to the input of said amplifier means; third and fourth switch means coupled to said E2 signal means; third and fourth resistor means, each coupling the associated third and fourth switch means, respectively, to the input of said amplifier means; +I1 signal means coupled to said E1 signal means for generating a +I1 current signal; switch logic means selectively enabling said first, second, third and fourth switch means for changing the gain of said amplifier means and generating a corresponding change in said E3 voltage signal; means coupled to said amplifier means and generating a -I2 current signal from said -E3 voltage signal and coupled to said +I1 signal means and responding to the difference between said +I1 and -I2 current signals for controlling said switch logic means.
 2. In a shaft-angle to digital-data converter wherein E1 and E2 signals which are representative of first and second trigonometric functions, respectively, of said shaft angle theta , are through the successive approximation method converted to a multibit data word held in a data register, which data word is representative of said shaft angle theta , using a ladder network having a reference -E3 signal input for converting the approximated data word held in the data register to a -I2 signal and a resistor network for converting said E1 signal to a +I1 signal, a comparator for compAring said +I1 and -I2 signals and generating a binary output that is representative of said comparison, and control logic for changing said approximated data word in said data register in response to said binary output, the improvement comprising: E1 signal means for providing an E1 voltage signal that is representative of a first trigonometric function of said shaft angle theta ; E2 signal means for providing an E2 voltage signal that is representative of a second trigonometric function of said shaft angle theta ; amplifier means for providing at its output a -E3 voltage signal in response to said E1 and E2 voltage signals; first and second switch means coupled to said E1 signal means; first and second resistor means each coupling the associated first and second switch means, respectively, to the input of said amplifier means; third and fourth switch means coupled to said E2 signal means; third and fourth resistor means, each coupling the associated third and fourth switch means, respectively, to the input of said amplifier means; fifth resistor means coupling said E1 signal means to the input of said amplifier means; sixth resistor means coupling said E2 signal means to the input of said amplifier means; seventh resistor means intercoupling the input and output of said amplifier means; means coupled to said data register selectively enabling said first, second, third and fourth switch means in response to said approximated data word for changing the gain of said amplifier means and coupling a correspondingly changed -E3 signal to said ladder network.
 3. In a shaft-angle to digital-data converter, the apparatus comprising: E1 signal means for providing an E1 voltage signal that is representative of a first trigonometric function of said shaft angle theta ; E2 signal means for providing an E2 voltage signal that is representative of a second trigonometric function of said shaft angle theta ; amplifier means for providing at its output a -E3 voltage signal in response to said E1 and E2 voltage signals; a first plurality of switch means coupled to said E1 signal means; a first plurality of resistor means for parallely coupling an associated one of said first plurality of switch means to the input of said amplifier means; a second plurality of switch means coupled to said E2 signal means; a second plurality of resistor means for parallely coupling an associated one of said second plurality of switch means to the input of said amplifier means; a resistor ladder network for providing at its output a -I2 current signal; means coupling said -E3 voltage signal output of said amplifier means to the input of said ladder network; a comparator; means coupling said -I2 current signal output of said ladder network to said comparator; means including a resistor means for coupling a +I1 current signal from said E1 signal means to said comparator; said comparator comparing said +I1 and -I2 current signals and alternatively providing at its output a first and a second one of a binary signal that is representative of said comparison; control logic means; data register means for holding a multibit data word; means for coupling said binary signal to said control logic means; means coupling said control logic means to said data register means for changing said multibit data word held in said data register means in response to said binary signal; means coupling said data register means to said first and second plurality of switch means for selectively enabling said first and second plurality of switch means in response to said changing multibit data word held in said dAta register and changing said -E3 voltage signal in response thereto; and, means coupling said data register means to said ladder network for enabling both said changing multibit data word held in said data register means and said changing -E3 voltage signal to generate a corresponding change in said -I2 current signal. 